The present invention relates to a semiconductor device and a manufacturing method thereof, and may be preferably used for, for example, a semiconductor device having a nonvolatile memory, and a manufacturing method thereof.
As one of electrically writable/erasable nonvolatile memories, namely, EEPROMs (Electrically Erasable and Programmable Read Only Memories) which are nonvolatile semiconductor storage devices, flash memories have been widely used. The flash memories each have a conductive floating gate electrode surrounded by an oxide film and a trapping insulation film under a gate electrode of MISFET (Metal Insulator Semiconductor Field Effect Transistor). Further, the flash memory stores information by using a difference in threshold voltage of a MISFET caused by the presence or absence of charges, namely, electrons or holes in the floating gate electrode or the trapping insulation film. In a semiconductor device as such a nonvolatile memory, memory cells forming the nonvolatile memory are formed in a memory cell region over a semiconductor substrate.
WO 2010/82389 (Patent Document 1) discloses as follows: a memory cell has a first gate insulation film, a selection gate electrode formed over the first gate insulation film, and a memory gate electrode formed over one side surface of the selection gate electrode. Further, Patent Document 1 discloses as follows: the memory cell has a second gate insulation film formed between the selection gate electrode and the memory gate electrode, and between the memory gate electrode and the semiconductor substrate.
Japanese Unexamined Patent Publication No. 2003-249579 (Patent Document 2) discloses as follows: the memory cell has a two-layer gate structure including a gate insulation film, a floating gate layer, a control gate layer, and an insulation film for electrically insulating the floating gate layer and the control gate layer.